Electronic devices, such as tablets, computers, copiers, digital cameras, smart phones, control systems and automated teller machines, among others, often employ electronic components which leverage chip package assemblies for increased functionality and higher component density. Conventional chip packaging schemes often utilize a package substrate, often in conjunction with a through-silicon-via (TSV) interposer, to enable a plurality of integrated circuit (IC) dies to be mounted to a single package substrate. The IC dies may include memory, logic or other IC devices.
Out of plane deformation of the package substrate, i.e., warpage, can be problematic to conventional chip packaging schemes. Warpage is particularly problematic in conventional chip packaging schemes that have an asymmetrical die distribution about at least one of the horizontal axes. Such warpage or bending of the package substrate can lead to solder connection failure or other damage to the components and devices of the chip package assembly, which may detrimentally effect device performance and reliability.
In many instances, dummy dies are utilized to stiffen the package substrate against out of plane deformation. The use of dummy dies is particularly common on chip packages that integrate high band-width memory (HBM) with field programmable gate arrays (FPGA). However, dummy dies undesirably increase the cost of the chip package. Additionally, die attach films often utilized to attach the dummy dies to an underlying substrate typically have high coefficients of thermal expansion (CTE), which undesirably contributes to delamination and crack initiation.
Therefore, a need exists for an improved chip package assembly, and in particular, to a chip package assembly having a conformal lid.